1. Field of the Invention
The present invention relates to a semiconductor device in which multiple bits of data can be programmed and a programming method thereof.
2. Description of the Related Art
The semiconductor device such as a non-volatile semiconductor device is designed to have a large capacity with the advancements of the processing technology. Programming and erasing are increasingly demanded to be faster in accordance with the large capacity of the semiconductor device.
In a flash memory, all the bits have to be programmed before erasing, and so an increase in the programming speed increases the erasing speed. This is because multiple data are programmed by one byte (eight bits) or one word (16 bits) simultaneously.
However, adjacent memory cells on the same word line share the bit line in the non-volatile semiconductor device of a virtual ground type. If a distance is too short between the memory cells in which multiple bits are programmed simultaneously, there arises a problem in that a stress caused by programming is applied to other memory cells in which nothing is to be programmed.
FIG. 1 shows virtual ground type memory cells 0 through 4 that are connected to a word line WL and share bit lines. FIG. 1 also shows metal bit lines MBL 0 through MBL 5 connected to drain regions and source regions of the memory cells 0 through 4, selector switches Ssel 0 through Ssel 5 that respectively connect the metal bit lines MBL 0 through MBL 5 to a ground line, and selector switches Dsel 0 through Dsel 5 that respectively connect the metal bit lines MBL 0 through MBL 5 to a data line. Here, FIG. 1 shows only a portion of the non-volatile semiconductor device that is necessary for description.
For example, assuming that the metal bit line MBL 0 is set to a low level and the metal bit line MBL 1 is set to a high level so as to write data into the memory cell 0. At the same time, assuming that the metal bit line MBL 2 is set to the low level and the metal bit line MBL 3 is set to the high level so as to write data into the memory cell 2. Here, the memory cell 1 interposed by the memory cell 0 and the memory cell 2 connects the gate thereof to the word line WL, which is also shared by the memory cell 0 and memory cell 2. The metal bit line MBL1 is set to the high level and the metal bit line MBL 2 is set to low level, and the data is also written in the memory cell 1. That is to say, the stress caused by writing is applied to the memory cell into which data does not have to be written.